The present invention relates to a semiconductor device and, more particularly, to a compact and low-profile sealed semiconductor device formed by bonding a semiconductor chip to a lead frame through bumps.
Electronic apparatuses are required to be compact and lightweight, and a semiconductor device to be mounted in an electronic apparatus is also required to be compact and low-profile.
For a conventional semiconductor device, a semiconductor chip is bonded to leads by wire bonding. This technique is not suitable for a low-profile semiconductor device because wires are looped and must be covered with a resin. In addition, since the wires have an inductance component, a high-frequency semiconductor chip becomes poor in high-frequency characteristics.
To solve these problems, a technique of connecting a semiconductor chip to leads through bumps is known. In, e.g., Japanese Patent Laid-Open No. 7-201928 (to be referred to as "prior art 1" hereinafter), a semiconductor chip is mounted on a TAB tape and sealed with a resin. Generally, a conductive pattern having a film-like tape shape is used as leads for a TAB tape, and these leads are as thin as 20 to 50 .mu.m. Because of the thin leads, a film carrier (3b in FIG. 1 of prior art 1) is required to keep a high mechanical strength, resulting in an increase in manufacturing cost.
To mount the semiconductor chip on a printed circuit board and solder them, the leads must be extracted from the resin-sealed portion. However, since one surface of each lead is covered with the film, the soldering properties degrade. If the film is removed to improve the soldering properties, outer leads are readily bent, so the solder is not connected to the printed circuit board or short-circuited to other printed patterns. As described above, the semiconductor device formed using the TAB tape is inconvenient to use for surface mounting.
Another semiconductor IC device is disclosed in Japanese Patent Laid-Open No. 1-128893 (to be referred to as "prior art 2" hereinafter). FIG. 7A shows a chip mounted on a lead frame 91 through bumps 93. This prior art has as its object to obtain a low-profile semiconductor IC device. FIG. 7B shows the section of the device.
In this semiconductor IC device, an IC chip 92 matches facedown each chip mounting piece 912 formed at one end of each of the plurality of leads 91 and is directly connected to the leads 91 through the bumps 93. The IC chip 92 is sealed with a molded body 94 together with the leads 91 each having a bent portion 911.
When the IC chip 92 and the leads 91 having the bent portions 911 are to be sealed, a lower surface 913 of the chip mounting piece 912 is exposed from the lower surface of the molded body 94. This lower surface 913 (exposed surface) of the chip mounting piece 912 functions as an external connection terminal. The exposed surface 913 also functions as a heat dissipation surface for removing heat from the IC chip 92.
FIG. 1B of Japanese Patent Laid-Open No. 5-129473 (to be referred to as "prior art 3" hereinafter) shows a chip-size package. In prior art 3, a semiconductor chip is mounted on rectilinear inner leads through bumps and sealed with a sealing member.
However, the conventional semiconductor devices have the following problems.
The first problem is connection between the semiconductor chip and the lead frame in the manufacturing process. As shown in FIG. 2 of prior art 2, when an IC chip 1 is mounted on a lead frame 2 before resin sealing, the IC chip 1 and the lead frame 2 are connected only through bumps. If external mechanical vibration, impact, or thermal stress is applied in the manufacturing process, disconnection occurs to result in an electrical connection failure. More specifically, the stress applied to the bumps includes vibration generated upon conveying the lead frame, an impact generated upon placing the lead frame on a working table or picking up it, a stress due to thermal expansion of the lead frame in thermal bump bonding or contraction in cooing the lead frame, and a stress due to deformation in moving the lead frame. Especially, in prior art 2, when an impact is applied from the short-side direction of the lead frame, a strong impact is readily transmitted to the bumps because of the short distance between leads 3 and the bumps.
In the semiconductor IC of prior art 2, the lower surface (exposed surface 913) of the chip mounting piece 912 connected to the IC chip 92 through the bump 93 is exposed from the molded body 94 as an external connection terminal, as shown in FIG. 7B. For this reason, connection to the IC chip 92 may become loose or peeling may occur due to a mechanical impact to result in an electrical contact failure.
As the second problem, in the semiconductor IC device of prior art 2, the lower surface 913 of the chip mounting piece 912 on which the IC chip 92 is mounted is exposed from the lower surface of the molded body 94 as an external connection terminal. For this reason, the leakage path for external moisture has a very short length corresponding to the thickness of the chip mounting piece 912, resulting in poor humidity resistance.
In addition, in the semiconductor IC device of prior art 2, the molded body 94 incorporates the bent portions 911 formed at the leads 91 to prevent removal of the chip mounting piece 912. Since the IC chip 92 is mounted on the recessed side of the leads 91 when viewed from the side surface, the bent portions 911 must be formed in consideration of the two-dimensional size of the IC chip 92 and the mounting position accuracy with respect to the two-dimensional size. Therefore, the two-dimensional size of the molded body 94 becomes larger than the interval between the chip mounting pieces 912 functioning as external connection terminals because the two-dimensional size of the molded body 94 cannot be made close to the size of the IC chip 92, resulting in an increase in mounting area of the printed circuit board.
As the third problem, in the resin-sealed surface-mounted semiconductor device of prior art 3, rectilinear outer leads with their upper and side surfaces being covered with a resin are used, so the leads are sometimes removed from the sealing member. In addition, the lead interval is determined by the electrode interval of the semiconductor chip. For this reason, for a small signal transistor having a semiconductor chip with a size of 0.5 mm.quadrature., the interval between leads is as small as about 0.1 mm. If such a package is mounted on a printed circuit board, a solder bridge is readily generated. Inversely, to increase the lead interval, the size of the semiconductor chip must increase, resulting in an increase in cost.